• 師資陣容

    • 行政技術人員

范倫達 Lan-Da Van 副教授
  • 國立台灣大學電機工程博士
  • 工程三館 419
  • 03-5712121 # 54815

經歷

1. Associate Professor, Dept. of Computer Science, NCTU, 2011-present
2. Assistance Professor, Dept. of Computer Science, NCTU, 2006-2011
3. Deputy Department Manager, National Chip Implementation Center (CIC), 2004-2006
4. Associate Researcher, National Chip Implementation Center (CIC), 2001-2006

研究興趣

3D繪圖系統與晶片設計、低功率/高效能DSP設計、物聯網系統與應用

實驗室

  • 超大型積體電路資訊處理實驗室
  • 工程三館 615
  • 03-5712121 # 54742

研究計畫

1. NCTU Project of Research Competency Enhancement for Young Professor: Power-efficient On-line Multi-mode Hilbert-Huang Transform Hardware Design and Implementation for Biomedical Signals: PI
2. An Embedded Multi-Core System for Client Side Graphics Applications: A Programmable 3D Graphics Processor Design for Client-Side Multi-Core Embedded Systems: Sub-Project PI(2011/5-2014/7),NSC
3. Next Generation Intelligent Intensive Care Unit Health-Care Systems: Design Integration of Biomedical Signal Processor and Multiple Biomedical Information Display based on Next-Generation Intelligent ICU: Sub-Project PI(2011/5-2014/7),NSC

代表著作

1. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, “General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry,” Multidimensional Systems and Signal Processing, accepted, 2013.
2. Lan-Da Van, D. Y. Wu, and C. S. Chen, “Energy-efficient FastICA Implementation for biomedical signal separation, IEEE Trans. Neural Networks, vol. 22, no. 11, pp. 1809-1822, Nov. 2011. (SCI & EI, Full Paper)
3. Lan-Da Van, and T. Y. Sheu, “A power-area efficient geometry engine with low-complexity subdivision algorithm for 3D graphics system, IEEE Trans. Circuits Syst. I: Regular Papers, vol. 58, no. 9, pp. 2211-2224, Sep. 2011. (SCI & EI, Full Paper)
4. D. Y. Wu and Lan-Da Van, “Efficient detection algorithms for MIMO communication systems,” Journal of Signal Processing Systems, vol. 62, no. 3, pp. 427-442, Mar. 2011. (SCI & EI, Full Paper)
5. P. Y. Chen, Lan-Da Van, I. H. Khoo, H.C. Reddy, C. T. Lin, “Power-efficient and cost-effective 2-D symmetry filter architectures,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 58, no. 1, pp. 112-125, Jan. 2011. (SCI & EI, Full Paper)
6. J. H. Tu and Lan-Da Van, “Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers,” IEEE Trans. Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009. (SCI & EI, Full Paper)
7. C. T. Lin, Y. C. Yu, and Lan-Da Van, “Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor,” IEEE Trans. VLSI Systs., vol. 16, no. 8, pp. 1058-1071, Aug. 2008. (SCI & EI, Full Paper)
8. Lan-Da Van, C. T. Lin, and Y. C. Yu, “VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 8, pp. 1644-1652, Aug. 2007. (SCI & EI, Full Paper)
9. M. A. Song, Lan-Da Van, and S. Y. Kuo, “Adaptive low-error fixed-width Booth multipliers,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007. (SCI & EI, Full Paper)
10. Lan-Da Van, and C. C. Yang, “Generalized low-error area-efficient fixed-width multipliers,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 1608-1619, Aug. 2005. (SCI & EI, Full Paper, NSC-93-2220-E-492-003)
11. Lan-Da Van, “A new 2-D systolic digital filter architecture without global broadcast,” IEEE Trans. VLSI Systs., vol. 10, pp. 477-486, Aug. 2002. (SCI & EI, Full Paper)